Integrated circuit devices can have input buffers to convert analog data input signals into full-rail complementary metal-oxide-semiconductor (CMOS) signals. For single-ended input signals, the transition from a logic ‘high’ to a logic ‘low’ is dependent on when the input signal crosses a reference voltage. A differential amplifier may detect the transition of the input signal across the reference voltage.
A metal-oxide-semiconductor (MOS)-based self-biased differential amplifier can convert input signal swings of less than 100 millivolts to full-rail signals. However, as the frequency of the input signal approaches 1 GHz, the gain of the MOS-based self-biased differential amplifier can roll off. This loss in gain can compromise the capacity of the MOS-based self-biased differential amplifier to convert the input signal into a full-rail output signal.
Current Mode Logic (CML) input buffers can be used for an input-output (I/O) interface. CML input buffers achieve increased speeds by limiting a swing of an output signal. However, CML input buffers require external biasing, which comes at the cost of substantial layout area and power requirements. Further, CML bias currents can be several times higher than a bias current for a MOS-based self-biased differential amplifier.